PCI Express* Architecture Power Management
PCI Express* Architecture Power Management
PCI Express* Architecture Power Management Rev 1.1
This paper presents power management gu >. identified for each link power state. L1 entry policy is also recommended to optimize device power. Several power optimization techniques are described, including minimizing flow control updates and acknowledgement packets to improve bandwidth efficiency, and pipelining packets to increase opportunities for active state link power management. These power management guidelines enable architectural innovation to achieve power-optimized interconnect performance.
Purpose of the document and target audience: This document is a collection of guidelines and recommendations for Intel-based Mobile PC platforms with PCI Express interconnect technology. The intent is to provide information that will improve PCI Express architecture enabled notebook performance while at the same time minimizing power consumption to reduce thermal problems and to maximize battery life. This is by no means intended to be a comprehensive description of all possible optimizations. It is also not intended to be used as a standard or specification. The target audience for this document is architects, engineers, and system developers whose role is to develop devices or systems incorporating PCI Express technology.
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Active-state power management (ASPM) is a power management mechanism for PCI Express devices to garner power savings while otherwise in a fully active state. Predominantly, this is achieved through active-state link power management; i.e., the PCI Express serial link is powered down when there is no traffic across it. It is normally used on laptops and other mobile Internet devices to extend battery life.
As serial-based PCIe bus devices, such as IEEE1394 (FireWire), become less active, it is possible for the computer’s power management system to take the opportunity to reduce overall power consumption by placing the link PHY into a low-power mode and instructing other devices on the link to follow suit. This is usually managed by the operating system’s power management software or through the BIOS, thus different settings can be configured for laptop battery mode versus running from the battery charger. Low power mode is often achieved by reducing or even stopping the serial bus clock as well as possibly powering down the PHY device itself.
While ASPM brings a reduction in power consumption, it can also result in increased latency as the serial bus needs to be ‘woken up’ from low-power mode, possibly reconfigured and the host-to-device link re-established. This is known as ASPM exit latency and takes up valuable time which can be annoying to the end user if it is too obvious when it occurs. This may be acceptable for mobile computing, however, when battery life is critical.
Currently, two low power modes are specified by the PCIe 2.0 specification; L0s and L1 mode. The first mode (L0s) concerns setting low power mode for one direction of the serial link only, usually downstream of the PHY controller. The second mode (L1) is bidirectional and results in greater power reductions though with the penalty of greater exit latency.
